Digital satellite TV broadcasting by a hierarchical transmission method is being developed toward practical use in which digital waves modulated by a plurality of modulation methods having different necessary C/N values, such as 8PSK modulated waves, QPSK modulated waves, and BPSK modulated waves, are multiplexed in time and repetitively transmitted one frame after another.
FIG. 9A is a diagram showing an example of the frame structure used by the hierarchical transmission system. One frame is constituted of: a BPSK modulated frame sync pattern (BPSK) of 32 symbols (of 32 symbols, the last 20 symbols are actually used as the frame sync signal); a BPSK modulated transmission and multiplexing configuration control pattern (TMCC) of 128 symbols for transmission multiplexing configuration identification; a super-frame identification information pattern of 32 symbols (of 32 symbols, the last 20 symbols are actually used as the super-frame identification signal); an 8PSK modulated (trellis codec 8PSK) main signal (TC8PSK) of 203 symbols; a burst symbol signal (BS) of 4 symbols which is a BPSK modulated pseudo random noise (PN) signal; an 8PSK modulated (trellis codec 8PSK) main signal of 203 symbols; a burst symbol signal (BS) of 4 symbols which is a BPSK modulated pseudo random noise (PN) signal; . . . ; a QPSK modulated main signal of 203 symbols; a burst symbol signal (BS) of 4 symbols which is a BPSK modulated pseudo random noise (PN) signal; a QPSK modulated main signal of 203 symbols; and a BPSK modulated burst symbol signal (BS) of 4 symbols, in this order.
In a receiver for receiving a digital modulated wave (PSK modulated wave) of the hierarchical transmission method, an intermediate frequency signal of a reception signal received by a receiver circuit is demodulated by a demodulation circuit to obtain I and Q baseband signals (hereinafter, the I and Q baseband signals are described also as I and Q symbol stream data) of two series representative of instantaneous values of symbols, of orthogonal land Q-axes. A frame sync signal is captured from the demodulated I and Q baseband signals. A current reception signal phase rotation angle is calculated from the signal point arrangement of the captured frame sync signal. In accordance with the calculated reception signal phase rotation angle, the demodulated I and Q baseband signals are rotated in the inverse phase direction to make the reception signal phase angle be coincident with the transmission signal phase angle. This absolute phasing is realized by an absolute phasing circuit.
As shown in FIG. 10, the absolute phasing circuit of a receiver for receiving a PSK modulated wave of a conventional hierarchical transmission method, is constituted of: a frame sync detection/reproduction circuit 2 which functions as a frame sync signal capturing means provided on the output side of a demodulation circuit 1 in order to capture a frame sync signal; a remapper 7 made of a ROM which functions as an inverse phase rotating means; and a reception signal phase rotation angle detection circuit 8 which functions as a reception signal phase rotating angle detecting means. A transmission configuration identification circuit identifies the transmission multiplex configuration shown in FIG. 9A and outputs a modulation method identification signal DM of two bits.
The demodulation circuit 1 orthogonally detects the intermediate frequency signal to obtain I and Q baseband signals.
In the demodulation circuit 1, a carrier reproduction circuit 10 reproduces two orthogonal reference carriers fc1 (=cos ωt) and fc2 (=sin at) shifted by 90° in phase and synchronized with the frequency and phase of the received carrier. Multipliers 60 and 61 multiply the intermediate frequency signal 1F and fc1 and fc2. A/D converters 62 and 63 A/D convert the outputs of the multipliers 60 and 61 at a sample rate two times faster than the symbol rate. Digital filters 64 and 65 limit the band widths of the outputs of the A/D converters 62 and 63 by using digital signal processing. Thinning circuits 66 and 67 thin the outputs of the digital filers 64 and 65 at a half of the sampling rate of the A/D converters 62 and 63 to output I and Q baseband signals (I and Q symbol stream data) of two series representative of instantaneous values of symbols of the I- and Q-axes. The thinning circuits 66 and 67 output I and Q baseband signals I(8) and Q(8) of eight bits (2's complement) of quantization. The numerals in the parentheses of I(8) and Q(8) indicate the number of quantization bits, and I(8) and Q(8) may also be described simply as I and Q.
Mapping for each modulation method on the transmission side will be described with reference to FIGS. 11A-11C. FIG. 11A shows the signal point arrangement of the 8PSK modulation method on an l-Q phase plane (also called an I-Q vector plane or an I-Q signal space diagram). The 8PSK modulation method can transmit a digital signal (abc) of three bits by one symbol. There are eight combinations of bits constituting one symbol: (000), (001), (010), (011), (100), (101), (110), and (11). A digital signal of three bits is converted into signal points “0” to “7” on the transmission side I-Q phase plane as shown in FIG. 11A.
In the example shown in FIG. 11A, the bit train (000) is converted into the signal point “0”, the bit train (001) is converted into the signal point “1”, the bit train (011) is converted into the signal point “2”, the bit train (010) is converted into the signal point “3”, the bit train (100) is converted into the signal point “4”, the bit train (101) is converted into the signal point “5”, the bit train (111) is converted into the signal point “6”, and the bit train (110) is converted into the signal point “7”.
FIG. 11B shows the signal point arrangement of the QPSK modulation method on an I-Q phase plane. The QPSK modulation method can transmit a digital signal (de) of two bits by one symbol. There are four combinations of bits constituting one symbol: (00), (01), (10), and (11). In the example shown in FIG. 11B, the bit train (00) is converted into the signal point “0”, the bit train (01) is converted into the signal point “3”, the bit train (11) is converted into the signal point “5”, and the bit train (10) is converted into the signal point “7”.
FIG. 11C shows the signal point arrangement of the BPSK modulation method on an I-Q phase plane. The BPSK modulation method transmits a digital signal (f) of one bit by one symbol. For example, the bit (0) of the digital signal (f) is converted into the signal point “0” and the bit (1) is converted into the signal point “4”. The relation between the signal point arrangement and its point number of each modulation method is the same by using the relation of 8PSK as a reference.
The I- and Q-axes of QPSK and BPSK of the hierarchical transmission method are coincident with those of 8PSK.
If the phase of the reception carrier is coincident with the phase of the reference carriers fc1 and fc2 reproduced by the carrier reproduction circuit 10, the phase of the received signal point on the I-Q phase plane determined by the I and Q baseband signals I(8) and Q(8) is coincident with that on the transmission side, when the digital signal referenced to the signal point arrangement of “0” to “7” on the I-Q phase plane on the transmission side is received. Therefore, by using the relation (refer to FIGS. 11A-11C) between the signal point arrangement and a digital signal on the transmission side as it is, the received digital signal can be correctly identified from the signal point arrangement of the received signal point.
However, in practice, the reference carriers fc1 and fc2 can take various phase states relative to the received carrier, so that the received signal point takes a phase rotated by some angle θ relative to the transmission side. As the phase of the received carrier changes, this angle θ also changes. As the phase of the received signal point changes randomly relative to the transmission side, it is impossible to identify the received digital signal. For example, assuming that θ=n/8, a digital signal (000) at the signal point “0” on the transmission side by the 8PSK modulation method takes a received signal point just at the middle of the signal points “0” and “1”. In this case, if it is presumed that the signal was received at the signal point “0”, then the digital signal (000) can be received correctly.
However, if it is presumed that the signal was received at the signal point (001), then an error occurs that a digital signal (001) was received. From this reason, the carrier reproduction circuit 10 corrects the phase of the reference carriers fc1 and fc2 so as to maintain the received signal point at a predetermined rotation angle relative to the transmission side and correctly discriminate the digital signals.
More specifically, a VCO (voltage controlled oscillator) 11 of the carrier reproduction circuit 10 oscillates at a transmission carrier frequency to generate the reference carrier fc1. The reference carrier fc2 is generated by delaying the phase of the oscillation signal of VCO 11 by 90° by a phase shifter 12. By varying the control voltage to VCO 11, the phases of the reference carriers fc1 and fc2 can be changed.
The carrier reproduction circuit 10 has phase error tables 13, 14-1 and 14-2, and 15-1 to 15-4 made of ROM and corresponding to the modulation methods of 8PSK, QPSK and BPSK (refer to FIG. 12). Each table stores a correspondence between various data pairs of the I and Q baseband signals 1(8) and Q(8) and carrier phase error data ΔΦ(8) (hereinafter simply called also phase error data) having the quantization bit number of 8 bits (2's complement). Each of the tables 13, 14-1 and 14-2, and 15-1 to 15-4 is input with the I and Q baseband signals I(8) and I(8) in parallel. The phase error table selectively enabled by a selector to be described later outputs the phase error data ΔΦ(8) corresponding to the I and Q baseband signals I(8) and Q(8) input from the demodulation circuit 1.
The phase error table 13 is used for 8PSK. The relation between a phase angle Φ (refer to FIG. 13) and the phase error data ΔΦ(8) is shown in FIG. 15, the phase angle Φ being a phase angle of the received signal point on the I-Q phase plane determined by the I and Q baseband signals I(8) and Q(8) input from the demodulation circuit 1. While the demodulation circuit 1 demodulates the digitally modulated signal of BPSK modulation (this demodulation being designated by the modulation method identification signal DM of the transmission configuration identification circuit 9 to be later described), the selector 16 enables (activates) only the phase error table 13 and reads the phase error data ΔΦ(8) corresponding to the I(8) and Q(8) paired data, in response to a clock CLKSYB (refer to FIG. 9(B) of the symbol rate synchronized with the output of the I and Q base band signals 1(8) and Q(8) from the demodulation circuit 1, each time the demodulation circuit I outputs the I and Q baseband signals 1(8) and Q(8) of one symbol. The phase error data ΔΦ(8) is converted into a phase error voltage by a D/A converter 17, its low frequency components being removed by an LPF 18, and supplied to VCO 11 as its control voltage. If the phase error data ΔΦ(8) is 0, an output of LPF 18 does not change and the phases of the reference carriers fc1 and fc2 do not change. However, if the phase error data ΔΦ(8) is positive, the output of LPF 18 becomes large and the phases of the reference carriers fc1 and fc2 are delayed, or conversely, if the phase error data ΔΦ(8) is negative, the output of LPF 18 becomes small and the phases of the reference carriers fc1 and fc2 are advanced.
In the phase error table 13, a difference between Φ and the phase of the nearest signal point in the signal point arrangement of “0” to “7” is indicated by the phase error data ΔΦ(8). The digital signal on the transmission side by the 8PSK modulation method at the signal point having the phase 0, n/4, 2π/4, 3π/4, 4π/4, 5π/4, 6π/4, or 7π/4 is rotated on the I-Q phase plane on the reception side by Θ=m×n/4 (where m is an optional integer from 0 to 7, refer to FIG. 14). Θis a reception signal phase rotation angle. Since the received signal point of the 8PSK modulation method is positioned at the phase of 0, n/4, 2π/4, 3π/4, 4π/4, 5π/4, 6π/4, or 7π/4, the phase of the signal point arrangement of “0” to “7” on the I-Q phase plane on the reception side can be assigned to the same phase as the transmission side (depending upon Θ, the relation between the signal point arrangement and digital signal changes). By detecting Θ, an inverse phase rotation by −Θ is performed so that the relation between the signal point arrangement and digital signal can be made the same as the transmission side (absolute phasing) and the received digital signal can be easily discriminated.
The phase error tables 14-1 and 14-2 are used for QPSK. The relation between a phase angle Φ and the phase error data ΔΦ(8) is shown in FIGS. 16 and 17, the phase angle Φ being a phase angle of the received signal point on the I-Q phase plane determined by the I and Q baseband signals I(8) and Q(8). During the normal reception, while the demodulation circuit 1 demodulates the digital modulated signal of QPSK modulation, the selector 16 enables only the phase error table 14-1 and reads the phase error data ΔΦ(8) corresponding to the 1(8) and Q(8) paired data, if the reception signal phase rotation angle Θ is 0, 2π/4, 4π/4, or 6π/4, in response to the clock CLKSYB of the symbol rate and each time the demodulation circuit 1 outputs the I and Q baseband signals I(8) and Q(8) of one symbol.
In the phase error table 14-1, a difference between Φ and the phase of the nearest signal point in the signal point arrangement of “1”, “3”, “5” and “7” is indicated by the phase error data ΔΦ(8). The digital signal on the transmission side using the QPSK modulation method at the signal point “1”, “3”, “5”, or “7” having the phase n/4, 3π/4, 5π/4, or 7π/4 is rotated on the I-Q phase plane on the reception side by Θ. If Θ is 0, 2π/4, 2π/4, or 6π/4, the received signal point of the QPSK modulation method is at the phase of n/4, 3π/4, 5π/4, or 7π/4. By detecting Θ, an inverse phase rotation by −Θ is performed so that the relation between the signal point arrangement and digital signal can be made the same as the transmission side (absolute phasing) and the received digital signal can be easily discriminated.
While the demodulation circuit 1 demodulates the digital modulated signal of QPSK modulation, the selector 16 enables only the phase error table 14-2 and reads the phase error data ΔΦ(8) corresponding to the I(8) and Q(8) paired data, if the reception signal phase rotation angle Θis π/4, 3π/4, 5π/4, or 7π/4, each time the demodulation circuit 1 outputs the I and Q baseband signals I(8) and Q(8) of one symbol.
In the phase error table 14-2, a difference between Φ and the phase of the nearest signal point in the signal point arrangement of “0”, “2”, “4” and “6” is indicated by the phase error data ΔΦ(8). The digital signal on the transmission side using the QPSK modulation method at the signal point “1”, “3”, “5”, or “7” having the phase n/4, 3π/4, 5π/4, or 7π/4 is rotated on the I-Q phase plane on the reception side by Θ. If Θ is n/4, 3π/4, 5π/4, or 7π/4, the received signal point of the QPSK modulation method is at the phase of 0, 2π/4, 4π/4, or 6π/4. By detecting Θ, an inverse phase rotation by −Θ is performed so that the phase on the reception side can be made the same as the transmission side (absolute phasing), the relation between the signal point arrangement and digital signal can be made the same as the transmission side, and the received digital signal can be easily discriminated.
The phase error tables 15-1 to 15-4 are used for BPSK. The relation between a phase angle Φ and the phase error data ΔΦ(8) is shown in FIGS. 18 to 21, the phase angle Φ being a phase angle of the received signal point on the I-Q phase plane determined by the I and Q baseband signals I(8) and Q(8). While the demodulation circuit 1 demodulates the digital modulated signal of QPSK modulation, the selector 16 enables only the phase error table 15-1 and reads the phase error data ΔΦ(8) corresponding to the I(8) and Q(8) paired data, if the reception signal phase rotation angle Θ by the phase correction of the 8PSK modulation method is 0 or 4π/4, in response to the clock CLKSYB of the symbol rate and each time the demodulation circuit 1 outputs the I and Q baseband signals I(8) and Q(8) of one symbol. In the phase error table 15-1, a difference between Φ and the phase of the nearest signal point in the signal point arrangement of “0” and “4” is indicated by the phase error data ΔΦ(8). The digital signal on the transmission side using the BPSK modulation method at the signal point “0” or “4” having the phase 0, or 4π/4 is rotated on the I-Q phase plane on the reception side by Θ. If Θis 0 or 4π/4, the received signal point of the BPSK modulation method is at the phase of 0 or 4π/4.
While the demodulation circuit I demodulates the digital modulated signal of BPSK modulation, the selector 16 enables only the phase error table 15-2 and reads the phase error data ΔΦ(8) corresponding to the I(8) and Q(8) paired data, if Θ is n/4 or 5π/4, each time the demodulation circuit 1 outputs the I and Q baseband signals I(8) and Q(8) of one symbol.
In the phase error table 15-2, a difference between Φ and the phase of the nearest signal point in the signal point arrangement of “1” and “5” is indicated by the phase error data ΔΦ(8). The digital signal on the transmission side using the BPSK modulation method at the signal point “0” or “4” having the phase 0, or 4π/4 is rotated on the I-Q phase plane on the reception side by Θ. If Θ is n/4 or 5π/4, the received signal point of the BPSK modulation method is at the phase of n/4 or 5π/4.
While the demodulation circuit 1 demodulates the digital modulated signal of BPSK modulation, the selector 16 enables only the phase error table 15-3 and reads the phase error data ΔΦ(8) corresponding to the I(8) and Q(8) paired data, if Θ is 2π/4 or 6π/4, each time the demodulation circuit 1 outputs the I and Q baseband signals I(8) and Q(8) of one symbol.
In the phase error table 15-3, a difference between Φ and the phase of the nearest signal point in the signal point arrangement of “2” and “6” is indicated by the phase error data ΔΦ(8). The digital signal on the transmission side using the BPSK modulation method at the signal point “0” or “4” having the phase 0, or 4π/4 is rotated on the I-Q phase plane on the reception side by Θ. If Θ is 2π/4 or 6π/4, the received signal point of the BPSK modulation method is at the phase of 2π/4 or 6π/4.
While the demodulation circuit 1 demodulates the digital modulated signal of BPSK modulation, the selector 16 enables only the phase error table 15-4 and reads the phase error data ΔΦ(8) corresponding to the I(8) and Q(8) paired data, if Θ is 3π/4 or 7π/4, each time the demodulation circuit I outputs the I and Q baseband signals I(8) and Q(8) of one symbol.
In the phase error table 15-4, a difference between Φ and the phase of the nearest signal point in the signal point arrangement of “3” and “7” is indicated by the phase error data ΔΦ(8). The digital signal on the transmission side using the BPSK modulation method at the signal point “0” or “4” having the phase 0 or 4π/4 is rotated on the I-Q phase plane on the reception side by Θ. If Θ is 3π/4 or 7π/4, the received signal point of the BPSK modulation method is at the phase of 3π/4 or 7π/4. Also in the BPSK modulation, by detecting 0, an inverse phase rotation by −Θ is performed so that the phase on the reception side can be made the same as the transmission side (absolute phasing), the relation between the signal point arrangement and digital signal can be made the same as the transmission side, and the received digital signal can be easily discriminated.
The frame sync detection/reproduction circuit 2 has, as shown in FIG. 22, a BPSK demapper 3, sync detection circuits 40 to 47, a frame sync circuit 5, and an OR gate circuit 53, and a frame sync signal generator 6. The reception signal phase rotation angle detection circuit 8 has delay circuits 81 and 82, a 0°/180° phase rotation circuit 83, averaging circuits 84 and 85, and a reception phase judgement circuit 86.
The I and Q baseband signals I(8) and Q(8) output from the demodulation circuit 1 are input to, for example, the BPSK demapper 3 of the frame sync detection/reproduction circuit 2 for capturing the frame sync signal which was BPSK modulated. A BPSK demapped bit stream B0 is therefore output. The BPSK demapper 3 is made of, for example, a ROM.
Next, the frame sync signal will be described. In the hierarchical transmission method, the frame sync signal is BPSK modulated with a lowest necessary C/N and transmitted. The bit stream of the frame sync signal constituted of 20 bits is (SOS1, . . . , S18S19)=(11101100110100101000), these bits being sequentially transmitted starting from S0. The bit stream of the frame sync signal is described also as “SYNCPAT”. This bit stream is converted into the signal point “0” or “4” by the BPSK mapping shown in FIG. 11C on the transmission side, and the converted symbol stream is transmitted.
In order to capture 20 bits BPSK modulated and transmitted, i.e., the frame sync signal of 20 symbol marks, it is necessary to convert the received symbol into a bit by BPSK demapping shown in FIG. 23A in the manner opposite to the mapping on the transmission side. As shown in FIG. 23A, if the demodulated signal is received in a hatched area of the I-Q phase plane on the reception side, it is judged that the signal is “0”, whereas if it is received in an area other than the hatched area, it is judged that the signal is “1”. Namely, depending upon whether the signal is received in which one of the two judgement areas divided by a BPSK judgement border line indicated by a thick line in FIG. 23A, the output is judged as either “0” or “1”. In this manner, the BPSK demapping is performed.
The I and Q baseband signals I(8) and Q(8) are input to the BPSK demapper 3 to be subjected to the BPSK demapping and the BPSK demapper 3 outputs the BPSK demapped bit stream B0. In this specification, demapping is intended to mean a demapping circuit. The bit stream B0 is input to the sync detection circuit 40 which captures the bit stream of the frame sync signal from the sync detection circuit 40.
Next, the sync detection circuit 40 will be described with reference to FIG. 24. The sync detection circuit 40 has serially connected 20 D-type flip-flops (hereinafter described as D-F/F) D19 to DO which constitute a shift register of 20 steps. The bit stream B0 is input to D-F/F D10 and sequentially shifted up. At the same time, outputs from D-F/F D19 to DO are supplied to an AND gate 51, with predetermined bits being logically inverted. The AND gate 51 outputs a high level SYNA0 when the output state (D0D1, . . . , D18D19) becomes (11101100110100101000). Namely, when SYNCPAT is captured, SYNA0 takes a high level.
The output SYNA0 of the sync detection circuit 40 is input via the OR gate circuit 53 to the frame sync circuit 5. The frame sync circuit 5 judges that the frame synchronization was established if the output SYNA of the OR gate circuit repetitively took the high level at a predetermined frame period, and outputs a frame sync pulse at each frame period.
Generally, in the hierarchical transmission method by which signals modulated by a plurality of modulation methods having different necessary C/N are multiplexed in time and repetitively transmitted one frame after another, header data representative of the multiplex configuration is multiplexed (TMCC pattern shown in FIG. 9A). After the frame sync detection/reproduction circuit 2 judges that the frame synchronization was established, the transmission configuration discrimination circuit 9 derives TMCC indicating the multiplex configuration from the BPSK demapped bit stream input from the frame sync circuit 5, analyzes it and outputs the modulation method identification signal DM indicating the modulation method for the current I and Q base band signals, to the selector 16 and the like (refer to FIG. 9(B). Also, after the frame sync detection/reproduction circuit 2 judges that the frame synchronization was established, the reception signal phase rotation angle detection circuit 8 detects the reception signal phase rotation angle Θ in accordance with the reproduced sync signal output from the frame sync signal generator 6, and outputs a reception signal phase rotation angle signal AR of 3 bits to the remapper 7, a selector 16 of the carrier regeneration circuit 10, and the like.
After the modulation method identification signal DM is input from the transmission configuration identification circuit 9 and the reception signal phase rotation angle signal AR 3) is input from the reception signal phase rotation angle detection circuit 8, the selector 16 of the carrier reproduction circuit 10 reads the phase error data ΔΦ(8) from the phase error table corresponding to the modulation method and reception signal phase rotation angle Θ, and outputs it to the D/A converter 17. During the period before this operation, the selector 16 reads the phase error data ΔΦ(8) from the phase error table for 8PSK.
The demodulation circuit I therefore operates always as an 8PSK demodulation circuit until the transmission configuration identification circuit 9 discriminates the multiplex configuration and the reception signal phase rotation angle detection circuit 8 detects the reception signal phase rotation angle Θ. Therefore, depending upon the phase state of the reference carriers fc1 and fc2 reproduced by the carrier reproduction circuit 10 of the demodulation circuit 1, the received signal point rotates in phase by Θ=m×π/4 (m is an integer of 0 to 7).
More specifically, as shown in FIG. 11C, depending upon the phase state of the reference carriers fc1 and fc2, the received signal point of the symbol stream of the frame sync signal BPSK mapped to the signal point “0” for the bit “0” and the signal point “4” for the bit “1” may take one of the following eight phase states for the demodulated frame sync signal. The eight phase states include: the signal points “0” and “4” at Θ=0 same as the transmission side; the signal points “1” and “5” rotated by Θ=n/4 in phase; the signal points “2” and “6” rotated by Θ=2π/4 in phase; the signal points “3” and “7” rotated by e=3π/4 in phase; the signal points “4” and “0” rotated by 8=4π/4 in phase; the signal points “5” and “1” rotated by Θ=5π/4 in phase; the signal points “6” and “2” rotated by Θ=6π/4 in phase; and the signal points “7” and “3” rotated by =7π/4 in phase. It is therefore necessary to capture the frame sync signal even if it is demodulated in any one of the phase states.
As shown in FIG. 25, the BPSK demapper 3 is therefore constituted of BPSK demappers 30 to 37 corresponding to the phase rotations of Θ=0 (m=0), Θ=n/4 (m=1), Θ=2π/4 (m=2), Θ=3π/4 (m=3), Θ=4π/4 (m=4), Θ=5π/4 (m=5), Θ=6π/4 (m=6), and Θ=7π/4 (m=7).
BPSK demapping shown in FIG. 23B shows that the symbol stream of the demodulated frame sync signal is rotated in phase by Θ=n/4, the bit “0” is at the signal point “1” and the bit “1” is at the signal point “5”. The BPSK judgement border line indicated by a thick line in FIG. 23B is rotated by n/4 in the counter-clockwise direction relative to the BPSK judgement border line indicated by the thick line in FIG. 23A of the BPSK demapping when the frame sync signal is received at the same phase as the transmission side. By using the BPSK demapper (at 31 in FIG. 25) for the BPSK demapping shown in FIG. 23B, the frame sync signal rotated in phase by Θ=π/4 can be captured stably. The bit stream BPSK demapped by the BPSK demapper 31 is an output B1 of the BPSK demapper 3 shown in FIG. 22.
Similarly, the BPSK demappers 32 to 37 execute demapping by using BPSK judgement border lines rotated by 2π/4, 3π/4, . . . , 7π/4 in the counter-clockwise relative to the BPSK judgement border line indicated by the thick line of the BPSK demapping shown in FIG. 23A. It is therefore possible to stably capture the frame sync signal rotated in phase by Θ=2π/4, 3π/4, . . . , 7π/4. The bit streams BPSK demapped by the BPSK demappers 32 to 37 correspond to outputs B2 to B7 of the BPSK demapper 3 shown in FIG. 22. The BPSK demapper-30 executes BPSK demapping by using the BPSK judgement border line indicated by the thick line of the BPSK demapping shown in FIG. 23A, so that the frame sync signal at Θ=0 can be stably captured. The bit stream BPSK demapped by the BPSK demapper 30 is an output B0 of the BPSK demapper 3 shown in FIG. 22.
The structure of the sync detection circuits 40 to 47 is similar to that of the sync detection circuit 40. With these sync detection circuits 40 to 47, irrespective of phase rotation of the baseband signals by the phase state of the reference carriers fc1 and fc2 reproduced by the carrier reproduction circuit 10 of the demodulation circuit 1, the frame sync signal can be captured by one of the sync detection circuits 40 to 47, and the high level SYNAn (n is an integer of 0 to 7) can be output from the sync detection circuit which captured the frame sync signal.
SYNAn signals output from the sync detection circuits 40 to 47 are input to the OR gate circuit 53 which outputs a logical sum SYNA of the signals SYNAn. The frame sync circuit 5 judges that the frame synchronization was established, if it is confirmed that the high level SYNA is repetitively input at the predetermined frame period, and outputs a frame sync pulse FSYNC at each frame period. In response to the frame sync pulse FSYNC output from the frame sync circuit 5, the frame sync signal generator 6 generates a bit stream (this is called a reproduced frame sync signal) same as the pattern SYNCPAT of the frame sync signal captured by the BPSK demapper 3, sync detection circuits 40 to 47 and frame sync circuit 5.
In the above description, the frame sync detection/reproduction circuit 2 shown in FIG. 22 captures the frame sync signal from the I and Q symbol stream data I(8) and Q(8) output from the demodulation circuit 1, and after a predetermined time delay, the frame sync signal generator 6 outputs the reproduced frame sync signal.
Next, the transmission configuration identification operation by the transmission configuration identification circuit 9 will be described. Input to the transmission configuration identification circuit 9 are bit streams B0 to B7 output from the BPSK demapper 3 of the frame sync detection/reproduction circuit 2, SYNA0 to SYNA7 output from the sync detection circuits 40 to 47, and a frame sync pulse FSYNC output from the frame sync circuit 5. When the frame sync pulse FSYNC is input, the bit stream Bn corresponding to one of SYNA0 to SYNA7 having repetitive high levels is read. By using a predetermined timing signal generated from the frame sync pulse FSYNC, the TMCC pattern shown in FIG. 9A is derived and analyzed.
Then, the modulation method identification signal DM indicating the modulation method for the current I and Q baseband signals I(8) and Q(8) is output (refer to FIG. 9(B)).
Next, a current reception signal phase rotation angle is obtained from the signal point arrangement of the captured frame sync signal. In accordance with the obtained reception signal phase rotation angle, the demodulated I and Q baseband signals I(8) and Q(8) are inversely rotated in phase. This absolute phasing will be described.
Each symbol of the symbol stream of the frame sync signal BPSK mapped at the transmission side and transmitted and then demodulated into the I and Q baseband signals I(8) and Q(8) by the modulation circuit 1 is demapped by the BPSK demapper 3 into the bit “0” or “1”. The symbol demapped into the bit “0” has a phase different of 180° from that of the symbol demapped into the bit “1”. The symbol demapped into the bit “1” in the frame sync signal of the received symbol stream is rotated in phase by 180° to obtain a symbol stream whose bits are all demapped into the bit “0”.
By calculating an average value for a plurality of symbols of the symbol stream whose bits are all demapped into the bit “0”, the reception signal point for the bit “0” of BPSK can be obtained. A phase difference is calculated between the reception signal point for the bit “0” of BPSK and the signal point “0” mapped into the bit “0” at the transmission side. This phase difference is used as the reception signal phase rotation angle Θ. The demodulated I and Q baseband signals are rotated in phase by η=−Θ to perform absolute phasing of the I and Q baseband signals I(8) and Q(8).
As described above, in response to the frame sync pulse from the frame sync circuit 5, the frame sync signal generator 6 generates the bit stream same as the pattern SYNCPAT of the captured frame sync signal, and supplies it as the reproduced frame sync signal to the 0°/180° phase rotation circuit 83 of the reception signal phase rotation angle detection circuit 8. The 0°/180° phase rotation circuit 83 rotates the I and Q baseband signals by 180° in phase for the bit “1” of the bit stream of the supplied reproduced frame sync signal, and does not rotate the I and Q baseband signals for the bit “0”.
The timing of the bit stream of the reproduced frame sync signal sent from the frame sync signal generator 6 and the timing of the symbol stream of the frame sync signal in the I and Q symbol streams are made coincident at the input side of the 0°/180° phase rotation circuit 0.83 by the delay circuits 81 and 82. The delay circuits 81 and 82 open their output gates only during the period while the frame sync signal generator 6 outputs a frame sync signal section signal. Therefore, the delay circuits 81 and 82 output the frame sync signal portions of the I and Q symbol streams DI(8) and DQ(8). The I and Q symbol streams DI(8) and DQ(8) are rotated by 180° in phase by the 0°/180° phase rotation circuit 83 for the symbol corresponding to the bit “1” in the bit stream of the reproduced frame sync signal, and are not rotated for the symbol corresponding to the bit “0”, to obtain symbol streams VI(8) and VQ(8) which are supplied to the averaging circuits 84 and 85. The symbol streams VI(8) and VQ(8) correspond to the symbol streams when a signal is received which signal was BPSK mapped on the transmission side assuming that all 20 bits constituting the frame sync signal are bits “0”.
FIG. 26A shows the signal point arrangement for the I and Q symbol streams I(8) and Q(8) of the frame sync signal received at the reception signal phase rotation angle Θ=0, and FIG. 26B shows the signal point arrangement for the I and Q symbol streams VI(8) and VQ(8) after converted by the 0/1800 phase rotation circuit 83. The I and Q symbol streams VI(8) and VQ(8) are supplied to the averaging circuits 84 and 85 and converted to have a quantization bit length of, for example, about 16 to 18 bits. Thereafter, the I and Q symbol streams are averaged for four frames (16×4=64 symbols), and the averaged values are output as AVI(8) and AVQ(8) having the original quantization bit length of 8 bits. Averaging the I and Q symbol streams VI(8) and VQ(8) is performed in order to obtain the stable signal point arrangement even if the phase and amplitude of the received baseband signals are changed slightly by degradation of reception C/N.
The received signal point [AVI(8), AVQ(8)] of the signal with the bit “1” BPSK mapped can be obtained by the averaging circuits 84 and 85. Next, the received signal point [AVI(8), AVQ(8)] is input to the phase judgement circuit 86 made of a ROM to obtain the reception signal phase rotation angle Θ in accordance with the reception signal phase rotation angle judgement table on an AVI-AVQ phase plane shown in FIG. 27. A phase rotation angle signal AR(3) of 3 bits (natural binary number) corresponding to 8 is therefore output. In FIG. 27, R=0 to 7 shows the decimal notation of the phase rotation angle signal AR(3). For example, the signal point of a point Z=[AVI(8), AVQ(8)] shown in FIG. 27 corresponds to the reception signal phase rotation angle 8=0 as judged by the reception signal phase rotation angle judgement table. Therefore, R =0, and (000) is output as the reception signal phase rotation angle signal AR(3). If the reception signal phase rotation angle Θ is n/4, then R=1 and (001) is output as the reception signal phase rotation angle signal AR(3).
Upon reception of the reception signal phase rotation angle signal AR(3), the remapper 7 made of ROM rotates the I and Q baseband signals I(8) and Q(8) by an angle corresponding to the reception signal phase rotation angle signal AR(3) to thereby perform absolute phasing.
The operation of the remapper 7 will be described. The remapper 7 constitutes a phase conversion circuit for making the signal point arrangement of the received I and Q baseband signals I(8) and Q(8) have the same signal point arrangement as the transmission side. The reception signal phase rotation angle detection circuit 8 calculates the reception signal phase rotation angle E and supplies the reception signal phase rotation angle signal AR(3) corresponding to the reception signal phase rotation angle κ to the remapper 7. The decimal notation R of the reception signal phase rotation angle signal AR(3) is an integer of 0 to 7, and the relation to the reception signal phase rotation angle Θ is defined by the following equation.R=Θ/(π/4)  (1) where 8=m×(n/4) and m is an integer of 0 to 7.
The absolute phasing for the I and Q baseband signals is performed by inverse rotation of the reception signal phase rotation angle Θ, i.e., by phase rotation of −Θ. Therefore, the remapper 7 rotates the input I and Q baseband signals I(8) and Q(8) by an angle η(=−Θ) in phase in accordance with the following equations (2) and (3), and outputs the absolute phased I and Q baseband signals I′(8) and Q′(8) (also described as I′ and Q′ by omitting the quantization bit number).I′=I cos (η)−Q sin (η)  (2) Q′=I sin (η)+Q cos (η)  (3) 
After the frame sync detection/reproduction circuit 2 captures the frame sync signal and the frame sync pulse is output, the transmission configuration identification circuit 9 may first identify the transmission configuration, and thereafter the reception signal phase rotation angle detection circuit 8 may detect the reception signal phase rotation angle. Or conversely, the reception signal phase rotation angle detection circuit 8 may first detect the reception signal phase rotation angle, and thereafter the transmission configuration identification circuit 9 may identify the transmission configuration. Alternatively, the reception signal phase rotation angle detection circuit 8 may detect the reception signal phase rotation angle concurrently with the identification of the transmission configuration by the transmission configuration identification circuit 9.
With the above-described conventional receiver, in order to correct the phase of the reference carriers fc1 and fc2 during the demodulation of QPSK modulation, two phase error tables 14-1 and 14-2 are required, and in order to correct the phase of the reference carriers fc1 and fc2 during the demodulation of BPSK modulation, three phase error tables 15-1 to 15-3 are required. A memory capacity required therefore becomes large.
An object of the invention is to provide a receiver capable of using a small circuit scale.